224G SerDes PCB Design

The 224G Challenge: Where Material Physics Meets Manufacturing Reality

The transition from 112G to 224G PAM4 SerDes represents a fundamental inflection point in PCB fabrication. At 112G (28 GHz Nyquist), Megtron 6 class materials with VLP copper deliver adequate performance for 6-8 inch channels. At 224G (56 GHz Nyquist), those same materials produce channels that cannot be equalized — the loss at Nyquist exceeds what even the most advanced DSP can recover. The PCB industry must deploy materials and processes that were exotic prototyping exercises just two years ago as volume production requirements.

The core problem is loss accumulation. At 56 GHz, every material imperfection, every rough copper grain boundary, every glass fiber in your prepreg contributes measurable insertion loss. A channel budget that had 5 dB of margin at 112G rates may show negative margin at 224G on identical physical geometry — because loss scales with frequency in a manner that compounds faster than linear. Dielectric loss increases proportionally with frequency (doubling from 28 to 56 GHz), but conductor roughness loss increases approximately as the square root of frequency, and radiation loss from discontinuities increases with the cube of frequency.

The result: what worked at 112G does not scale to 224G by simply choosing “better material.” The entire fabrication approach — material selection, copper specification, stackup architecture, via design, and process control — must be co-optimized as a system.

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Material Selection: The Df < 0.002 Threshold

For 224G PAM4 channels operating at 56 GHz Nyquist, the material dissipation factor threshold is approximately Df = 0.002 at 10 GHz for channels exceeding 4 inches. Below this threshold, the channel loss remains within the equalization capability of current-generation SerDes DSP (typically 35-40 dB of CDR/DFE/FFE capability). Above Df 0.002, even the best equalization cannot recover signal quality for typical switch-board channel lengths.

The material landscape for 224G-capable PCBs:

The material choice for 224G is not simply “pick the lowest Df” — manufacturing processability matters enormously. Megtron 7 retains FR-4-like processing (standard drill, plate, laminate), making it the practical choice for volume AI switch boards. PTFE offers lower loss but requires specialized drilling, plasma treatment, and bonding techniques that reduce yield and increase cost. For most 224G applications, Megtron 7 or Tachyon 100G provides the optimal balance of electrical performance and manufacturing feasibility.

Copper Roughness: The Dominant Loss Mechanism at 56 GHz

At 224G PAM4 operating frequencies, conductor roughness loss exceeds dielectric loss as the primary loss mechanism for ultra-low-loss materials. This creates a counterintuitive situation: switching from Megtron 6 to Megtron 7 material while keeping standard copper foil delivers only 30-40% of the expected loss improvement — because the copper roughness loss has not changed and now dominates the total.

The physics: current at 56 GHz is confined to a skin depth of approximately 0.28 um. Standard electrodeposited copper has treated-side roughness (Rz) of 5-8 um — meaning the current must navigate over peaks and valleys that are 20-30x deeper than the current penetration depth. The effective path length increase from this roughness adds loss according to the Huray or Hammerstad-Jensen models, typically contributing 0.3-0.5 dB/inch at 56 GHz on standard foil.

Copper foil options for 224G:

For 224G channels, HVLP is the minimum viable copper type. The difference between VLP and HVLP at 56 GHz is 0.06-0.10 dB/inch — over an 8-inch channel, that is 0.5-0.8 dB of channel loss. In a budget where total channel loss cannot exceed 30-35 dB (the equalization limit), every 0.5 dB matters enormously.

The manufacturing challenge with HVLP: smoother copper has lower peel strength (adhesion to laminate). Standard ED copper achieves 6-8 lb/inch peel strength; HVLP drops to 3-4 lb/inch. This reduced adhesion makes the copper more susceptible to delamination during thermal cycling, via drilling, and reflow soldering. Fabricators must adjust process parameters — reduced lamination pressure, modified microetch chemistry, and controlled drilling entry speed — to prevent adhesion failures. Not all manufacturers have validated their processes for HVLP foil on ultra-low-loss materials.

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Our process engineers have characterized HVLP copper on Megtron 7 with measured peel strength and insertion loss data. First-pass yield above 82% on 224G-class designs.

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Stackup Architecture for 224G Channels

The stackup for 224G-capable boards differs from conventional high-speed designs in several critical ways. Signal layer-to-reference distance must be tightly controlled (typically 3.0-3.5 mil on ultra-low-loss prepreg) for impedance targets. Every prepreg layer adjacent to a 224G signal must use spread glass to eliminate fiber weave skew. The stackup must minimize the number of layer transitions (via stubs are essentially prohibited at these frequencies), often requiring carefully planned signal layer assignments that avoid unnecessary transitions.

A representative 16-layer stackup for a 224G AI switch application:

Note the asymmetric material usage: only signal layers carrying 224G traffic use ultra-low-loss material and HVLP copper. Power planes and mid-speed signals use standard materials at a fraction of the cost. This hybrid material approach reduces total stackup material cost by 40-50% compared to all-ultra-low-loss construction, with negligible electrical penalty because power and ground planes do not carry high-frequency signal current.

Via Design: Zero-Stub Transitions at 56 GHz

At 224G PAM4 frequencies, via stubs are essentially unacceptable. Even a 3-mil residual stub creates a resonant notch that impacts the 56 GHz Nyquist region. The practical options for layer transitions in 224G designs are:

Blind/buried vias (preferred): Laser-drilled microvias or mechanically-drilled blind vias terminate exactly at the target layer with zero stub. This is the recommended approach for all 224G signal transitions. The cost premium of blind/buried via construction (HDI processing) is justified at these data rates because the alternative — backdrilling with ±2 mil tolerance — still leaves stub residual that may impact performance.

Precision backdrilling (acceptable with caveats): For transitions in conventional through-hole sections of the board, backdrilling to within ±2 mils of the signal layer is viable for 224G if the remaining stub is less than 3 mils. This requires: x-ray depth measurement feedback, controlled-depth spindle with impedance-sensing endpoint detection, and 100% inspection of backdrill depth on production panels. Not all fabricators can achieve ±2 mil consistently.

Via optimization (mandatory regardless of approach): The via anti-pad, pad size, and surrounding ground via arrangement must be impedance-optimized. A standard 20-mil via pad with 30-mil anti-pad creates a capacitive discontinuity that reflects 56 GHz signal energy. Optimized designs use reduced pad size (12-14 mil), enlarged anti-pad (35-40 mil), and tightly coupled ground return vias (6-8 ground vias within 30 mils of the signal via) to maintain 50-ohm impedance through the entire via transition.

From our fabrication data, the via transition loss contribution at 56 GHz:

Manufacturing Process Requirements

Producing 224G-capable boards requires process capabilities that go beyond standard PCB manufacturing. Here are the critical process parameters and what they demand from the fabrication facility:

Lamination profile control: Ultra-low-loss materials like Megtron 7 have narrower lamination process windows than standard FR-4. The resin flow must be precisely controlled to achieve target dielectric thickness (±0.3 mil versus ±0.5 mil for standard boards). Over-flow reduces dielectric thickness and increases impedance; under-flow creates resin-starved voids that increase loss. Our lamination presses use thermocouple monitoring at multiple panel positions with closed-loop temperature control to maintain ±2°C uniformity across the press opening.

Registration accuracy: At 3/3 mil trace/space on 0.5oz HVLP copper with tight impedance requirements, layer-to-layer registration must be within ±2 mils. Standard registration (±3-4 mil) is inadequate because registration error directly affects the trace-to-reference distance and thus impedance. We achieve ±1.5 mil registration using pin-lamination with optical alignment verification at each layer.

Etch uniformity: For 3.5 mil trace widths on HVLP copper, etch variation must be within ±0.3 mil across the panel. Standard spray etch with single-side nozzles achieves ±0.5-0.7 mil variation. We use horizontal etch with oscillating spray bars and in-line optical measurement to maintain ±0.25 mil uniformity — critical for delivering consistent impedance across all board positions in the panel.

Drill quality: Mechanical drills for via holes in ultra-low-loss laminate must avoid delamination at the entry and exit surfaces. HVLP copper’s lower adhesion makes it more susceptible to drill-exit burring. We use entry/exit material specifically selected for low-loss laminate processing and reduce spindle speed by 15-20% compared to standard FR-4 parameters.

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We manufacture 224G-class PCBs for AI switch, NIC, and optical transceiver applications. Megtron 7, HVLP copper, and validated channel loss data included with every quote.

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AI Data Center Application Context

The primary driver for 224G SerDes PCB technology is AI training and inference cluster interconnect. Current-generation AI accelerators (GPU and custom ASICs) use 112G PAM4 SerDes for chip-to-chip and chip-to-optical module connections. The next generation (shipping 2026-2027 from major silicon vendors) doubles to 224G PAM4 to meet the bandwidth demands of larger AI models requiring faster inter-GPU communication.

A typical AI switch board carries 128 lanes of SerDes at 224G, delivering 3.2 Tbps of aggregate bandwidth through a single chip package. The PCB must route these 128 lanes (64 differential pairs transmit + 64 receive) from the switch ASIC BGA to front-panel optical module cages — distances of 6-10 inches depending on switch architecture. At this channel length and data rate, the PCB is the limiting factor in system bandwidth. Material and manufacturing choices directly determine whether the system achieves its target BER of 1e-15 after FEC.

The economic reality: a single 224G AI switch board contains $800-1500 of PCB material and processing cost, but it enables a switch platform worth $30,000-80,000 that serves an AI cluster worth millions. The PCB cost premium for 224G-capable fabrication is a small fraction of system value, making it one of the highest-ROI investments in the entire data center bill of materials.

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From switch boards to NIC modules to optical transceiver substrates. Megtron 7, Tachyon 100G, and HVLP copper with validated 56 GHz insertion loss measurements on production panels.

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Reviewed by AtlasPCB Engineering Team — 15+ years in advanced PCB fabrication for RF, HDI, and rigid-flex applications.

Related Reading:

• AI Training Server PCB: 56G PAM4 Power Delivery Design
• Signal Integrity in PCB Design: Impedance Control, Crosstalk, Via Stubs
• PCB DFM Check for High-Speed Designs
• Megtron 6 vs Rogers 4350B: High-Frequency Laminate Comparison