Multilayer PCB Manufacturer 2 to 30 Layers, Precision Built

How We Build Your Stackup

Every multilayer PCB starts with stackup design, and we treat this as an engineering exercise — not a template lookup. The foundation is symmetry: a 12-layer board must be arranged so that layers 1-6 mirror layers 7-12 in copper weight, dielectric thickness, and prepreg type. Asymmetrical stackups bow and twist during lamination because unbalanced copper coverage creates differential stress as the resin cures. We check copper distribution on every layer pair and flag imbalances before production. If your design puts 80% copper fill on layer 3 but only 20% on layer 10, we will suggest copper thieving patterns to rebalance — or reorder the stackup to pair high-fill layers together.

Reference plane pairing drives signal integrity. Every high-speed signal layer sits adjacent to a continuous ground or power plane. In a typical 8-layer stackup, we arrange it as: Signal / Ground / Signal / Power / Power / Signal / Ground / Signal. The two inner signal layers (3 and 6) each have an uninterrupted reference plane immediately above and below them. This geometry creates a stripline structure with predictable impedance and good shielding from crosstalk. We never place two signal layers adjacent to each other without a plane between them — the coupling and impedance instability make it unworkable for anything above 1 Gbps.

Dielectric thickness control determines your impedance accuracy. After lamination, we hold prepreg thickness to ±0.5mil — meaning a 4.0mil target dielectric comes out between 3.5mil and 4.5mil. This tolerance directly feeds into impedance variation: on a 50-ohm single-ended trace at 5mil over ground, a ±0.5mil dielectric shift creates approximately ±4% impedance change. We select prepreg glass styles to minimize thickness variation: 1080 prepreg (2.8mil cured) has tighter thickness tolerance than 7628 (7.0mil cured) because thinner glass weaves compress more uniformly under press pressure. For critical impedance layers, we often specify two sheets of 1080 rather than one sheet of 2116, even though both hit similar total thickness — the dual-1080 approach gives better uniformity.

Material selection depends on your thermal and electrical requirements. Standard FR-4 at TG150 handles most applications with single lead-free reflow (peak 260°C). For boards facing multiple reflow cycles (double-sided assembly, rework), we specify TG170 which provides more thermal margin before glass transition — the resin stays rigid and dimensionally stable through 4-5 reflow passes. Isola 370HR (TG180, Td 340°C) is our go-to for aerospace and automotive where CAF resistance and long-term thermal reliability are critical. For high-speed digital above 10 Gbps, Panasonic Megtron 6 with Df 0.004 at 10GHz cuts insertion loss by 40% compared to standard FR-4 (Df 0.020) — the difference between a clean eye diagram and a closed one on a 12-inch trace at 25 Gbps.

Copper weight selection balances current capacity, etch capability, and cost. Inner layers typically run 0.5oz (17μm) for fine-pitch signal routing or 1oz (35μm) as the default for general routing and plane layers. For power distribution on high-current designs, we offer 2oz (70μm) inner layers — though trace width minimums increase from 3mil (at 0.5oz) to 5mil (at 2oz) because thicker copper undercuts more during etching. Outer layers start at 1oz base copper, built up to 1.5-2oz after pattern plating. Heavy copper boards (3oz-6oz) require modified etching parameters and wider annular rings, so we run DFM analysis early to confirm your design rules match the copper weight.

The lamination press cycle is where individual layers become a monolithic board. We load the book (stacked cores, prepregs, and copper foils) into a vacuum hydraulic press. The temperature ramp follows a precise profile: room temperature to 130°C at 2-3°C per minute (resin begins to flow), hold at 130°C for 15 minutes (ensures uniform flow across the panel), then ramp to 180°C at 2°C per minute (cross-linking begins), hold at 180°C for 60 minutes (full cure), then controlled cool-down at 3°C per minute to prevent thermal shock. Pressure starts at 50 PSI during flow stage, ramps to 300 PSI during cure, and holds until cool-down reaches 100°C. The entire cycle takes 3-4 hours per press load. Vacuum (below 10 mbar) runs throughout to eliminate entrapped air that would create voids between layers.

Impedance control on multilayer PCBs comes down to three variables we manage simultaneously: trace width, dielectric height (distance to reference plane), and copper weight (which affects trace cross-section after etching). A 50-ohm single-ended microstrip at 4mil dielectric height requires approximately 7mil trace width with 1oz copper. Change the dielectric to 3.5mil and the trace narrows to about 6mil. Change copper to 0.5oz and the trace widens to compensate for the thinner cross-section. We run impedance modeling (Polar Si9000) on every controlled-impedance stackup, then verify with TDR measurement on production coupons. The coupon sits on the same panel as your boards and goes through identical processing — giving real measured data, not just calculated predictions.

Buried and blind vias integrate naturally into multilayer construction. A buried via connects two inner layers — for example, layer 3 to layer 4 — and is drilled and plated before those layers get laminated into the full stackup. This means we fabricate the inner pair as a separate sub-lamination, drill, plate, and then incorporate it into the main press cycle. Blind vias connect an outer layer to an inner layer (e.g., layer 1 to layer 2) and are drilled after the final lamination using controlled-depth mechanical drilling or laser drilling for microvias. Both via types free up routing space: buried vias eliminate through-hole stubs that degrade high-speed signals, and blind vias let you route escape patterns without consuming real estate on all layers. We specify minimum annular ring of 4mil on blind/buried vias and verify registration layer-to-layer with X-ray alignment before drilling.

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